SEE/MAPLD Workshop Banner

29th Annual

Single Event Effects (SEE) Symposium coupled with the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop

Due to COVID-19 concerns, SEE/MAPLD has been postponed to October 4-7, 2020 and will remain at the La Jolla Marriott

San Diego, Marriott La Jolla

Late News Submission is Open!
Click Here for Details



Tutorial Speakers Announced

Draft Program Announced (Subject to change...)


Our Presentation Archive has been updated!
Now featuring over 700 talks spanning years 2006-2019
Jump to the Archives


SEE/MAPLD Needs Your Help
Sign up / encourage others to join our official email list for workshop announcements
(Opt-In; Managed by NASA/NEPP for Conference and Workshop Outreach)


Please join us for the jointly held

2020 Single Event Effects (SEE) Symposium and Military and Aerospace
Programmable Logic Devices (MAPLD) Workshop


New Dates: October 4 - 7, 2020

at the

Marriott LaJolla, CA, USA


Late News Abstract Submission is Open!

Submit your abstract here

Click Here for Registration Details



We are seeking contributions in the following areas, but all submissions will be reviewed. Four sessions are available: SEE, MAPLD, Combined, and Poster. The Combined Session includes submissions that cross SEE and MAPLD themes. The Poster Session can include SEE, MAPLD, or Combined content. Please refrain from technical content reasonably classified as product marketing.

SEE Symposium MAPLD
New! Artificial Intelligence (AI) / Machine Learning (ML) in FPGAs/SoCs: AI / ML design considerations for reliable terrestrial, avionic, and aerospace applications; using AI for SEE mitigation; SEE evaluation of designs leveraging AI / ML
Phenomena: Upsets, Functional Interrupts, Transients, Latchup, Gate Rupture, Burnout, etc. FPGAs/SoCs, PLDs, and New Devices: New and/or novel FPGA and PLDs; Benchmarking of FPGAs and PLDs; Applications of space-borne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Charge Transport and Collection, Impact of Circuit and Environmental Parameters, etc. Mitigation of Single event effects in FPGAs/SoCs, PLDs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), upset mitigation techniques and automated tools, etc.
SEE Mitigation Methods Including Radiation Hardened by Design (RHBD) and by Process (RHBP): Approaches for gaining SEE hardness in commercial devices, etc. Designing with FPGAs/SoCs, and PLDs: agile methods, ESL/HLS and model-based engineering techniques, embedded processing, and synthesis efficiency improvements.
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Pulsed Laser Test Facilities. Validation and Verification of FPGAs/SoCs, and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices from LEO to Interplanetary, High Altitude Aircraft, and Terrestrial. Availability/Reliability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data and Measurement Techniques: Memories, Analog/Digital Circuits, systems-on-chip (SoCs), Field Programmable Gate Arrays (FPGAs), Optocouplers, Photonic Integrated Circuits, Power Converters, Sensors, etc. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, etc.
Systems and Error Rate Computation: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems; Analytic, Monte Carlo, Mixed-Level, methods, etc. Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Education: Education Practices, Market Demands for Military and Aerospace Component Engineers, and Engineer Retention.
*All options subject to change any time, per the discretion of the conference committee

Notice: This program is in draft status and remains subject to change

2020 Workshop Schedule

Sat
Oct 3
Sun
Oct 4
Mon
Oct 5
Tue
Oct 6
Wed
Oct 7
Morning Technical
Sessions
Technical
Sessions
Technical
Sessions
Technical Sessions
Lunch Workshop
Lunch
Workshop
Lunch
Exhibit
Lunch
Exhibit
Lunch
Afternoon Break Exhibit
Setup
Exhibits Poster
Set Up
Evening Welcome
Reception
5:00
Free
Evening
Free
Evening
Exhibit
Reception
Posters and
Reception
5:00 - 9:00

Single-Event Effects Symposium - Technical Sessions

Lead Author

Institution

Title

Michael Campola

NASA Goddard Space Flight Center

Discrete Binning Analysis of Single Event Transient Pulse Width for Rate Calculations

Bernard Riemer

Oak Ridge National Laboratory

SEEMS - A New Facility for Single Event Effects Testing and Muon Spectroscopy

Razvan Gaza

NASA Johnson Space Center

The Radiation Assessment Matrix (RAM): A systematic approach to SEE circuit analysis in support of Single-Event Effects Criticality Assessment (SEECA)

Christopher Heistand

Johns Hopkins Applied Physics Laboratory

NVIDIA Jetson TX2i Radiation Report

Stephen Wender

Los Alamos National Laboratory

The LANSCE facility for measurement of neutron-induced failure in semiconductor devices

David Hansen

Data Device Corporation

A Track-Structure Based Approach to Upset-Rate Calculations

David Hansen

Data Device Corporation

Low and Medium Earth-Orbit Rates Using Design-of-Experiments and Monte-Carlo Methods

Joseph Cancelleri

University of Tennessee - Chattanooga

Analysis of Single Event Transients (SETs) using Machine Learning and Ionizing Radiation Effects Spectroscopy (IRES)

James Cannon

University of Tennessee - Chattanooga

Electrical Measurement of Cell-to-Cell Variation of Critical Charge in SRAM and Sensitivity to Single-Event Upsets by Low-Energy Protons

Eric Prebys

University of California - Davis, Crocker Nuclear Laboratory

Radiation Effects Facility at Crocker Nuclear Laboratory

Ashok Alagappan

ANSYS

Novel Approach to Modeling and Prediction of Single Event Upsets at Component Level

Jonathan Pellish

NASA Goddard Space Flight Center

Domestic Heavy Ion Single-Event Effects Test Facilities: Needs, Current Status, and Future

Michael Campola

NASA Goddard Space Flight Center

Single-Event Effects Criticality Assessment (SEECA) Guidance for Implementation

Steven Guertin

NASA Jet Propulsion Laboratory

Stuck Bits from Co-60, Electrons, Protons, and Heavy Ions

Daniele Monahan

The Aerospace Corporation

Recent Developments in Experimental Design for Pulsed X-ray SEE Testing

Ray Ladbury

NASA Goddard Space Flight Center

Data: What Are They Good For? (Absolutely...)

Single-Event Effects Symposium - Poster Presentations

Lead Author

Institution

Title

Kiran Bernard

Renesas Electronics America Inc.

SEE Testing of Renesas' Intersil Current Sense Amplifier

Kenneth LaBel

Science Systems and Applications, Inc.

Protons, Protons Everywhere - But Where Do We Test in the U.S.?

Combined Session - Oral Presentations

Lead Author

Institution

Title

Peter Ateshian

US Navy Naval Postgraduate School / Xtrm Designs, LLC

FPGA based MIMO optical spatio-temporal coding for soft error resilience in LPI LPD LPE communication

Joe Mallett

Synopsys

Fault Injection to Verify Functional Safety Logic

Nadia Rezzak

Microchip Technology

Heavy Ion and Proton Induced Single Event Effects on Microchip RT PolarFire FPGA

Patrick Fleming

Raytheon Space and Airborne Systems

Using Fault Injection to Predict the Error Rate of a Large Complex Design in a Non-Hardened SRAM-Based Xilinx 7-Series FPGA

Thomas Lange

iRoC Technologies / Politecnico di Torino

Error Rate Calculation of Functional Failures Induced by Single-Event Transients in Clock Distribution Networks

Matthew Cannon

Sandia National Laboratories

Fault Tracking and Modeling in Advanced Node Processors of Single Event Effects

Gary Swift

Swift Engineering and Radiation Services, LLC

Still Latched-up after All These Years: More Clues in the 7-Series FPGA Micro-Latchup Mystery

Allyson Yarbrough

The Aerospace Corporation

PMPedia (Parts, Materials, and Processes) Encyclopedia: A Crowd-Sourced Space Radiation Electronics Knowledge Repository

Combined Session - Poster Presentations

Lead Author

Institution

Title

Marco Leuenberger

Microchip Technology

Single Event Effects Characterization of Microchip Programmable Current Limiting Power Switch LX7712

Matt Von Thun

Cobham

Technology Evaluation for High Voltage Space Applications

Military and Aerospace Programmable Logic Devices Workshop - Oral Presentations

Lead Author

Institution

Title

Jyotika Athavale

Intel Corporation

The Power of Dense Silicon: Trending Features and Support at Chip-Level Enabling New Levels of Integration and Dependability for Avionics Systems

Mohamed El-Hadedy

California Polytechnic University

Performance evaluation of wide-range of AI applications on Rasberry Pi

Jacob Wiltgen

Mentor, A Siemens Business

Rethinking your approach to radiation mitigation

Scott Calkins

Blue Pearl Software

Using Static RTL Analysis to Accelerate Satellite FPGA Verification

Steve Parkes

STAR-Dundee LTD

Design and Test of SpaceFibre Interfaces in FPGAs

Kamesh Ramani

Mentor - A Siemens Business

Implementing Temporal Mitigation Solutions in FPGAs

David Merodio Codinachs

European Space Agency

ESA initial experiences of the NG-LARGE new capabilities: ARM Cortex-R5 and SERDES

Lucas Tambara

Cobham Gaisler AB

Development and FPGA Roadmap for LEON5FT and NOEL-V Processor Models

Jason Riddley

NASA Jet Propulsion Laboratory

Accelerating and Improving Design Reviews with Analysis Tools

Thomas Lange

iRoC Technologies / Politecnico di Torino

Towards the Use of Machine Learning to Estimate the Functional Failure Rate of Complex Circuits

Alric Althoff

Tortuga Logic

Executable Specifications for Hardware Assurance of SoCs and FPGAs

Military and Aerospace Programmable Logic Devices Workshop - Poster Presentations

Lead Author

Institution

Title

Maria Mitkova

Boise State University

Formation and Study of Nanotube Structure in Chalcogenide Glasses to Improve Speed, Reliability and Lifespan of CBRAM Devices

Mohamed El-Hadedy

California Polytechnic University

Reconfigurable Image Processing Applications on FPGAs

2020 SEE/MAPLD is pleased to announce the following tutorial sessions and speakers:


 

 

Fault-tolerance Concepts, Single Event Effects
Characterization, FPGA Scrubbing, and
Other Use Cases Using Industry Product Examples

 

This tutorial will focus on fault-tolerance concepts to allow uninterrupted software execution in the presence of correctable errors and SEE characterization results with the GR740 SoC and GR716 Microcontroller as product examples. The tutorial will also cover the development of the GRSCRUB FPGA scrubber IP core and its planned inclusion in the GR716 flight models.

 


Lucas Tambara

Cobham Gaisler

Lucas Antunes Tambara is a Component Engineer at Cobham Gaisler, Gothenburg, Sweden. He received his Ph.D. in Microelectronics and M.Sc. in Electrical Engineering from Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. He received his B.Sc. in Computer Science from Universidade Federal de Santa Maria (UFSM), Santa Maria, Brazil. His interests include radiation effects on integrated circuits, fault tolerance, embedded systems, and hardware design. Lucas has authored several publications in IEEE transactions and conferences, and also serves in the reviewer board of several international journals and frequently in the technical program committee for the RADECS and NSREC conferences.
 

 

 

Better FPGA Verification with Open Source
VHDL Verification Methodology (OSVVM)

 

Verification consumes a considerable amount of the FPGA development cycle. Using an effective verification methodology is important as it can improve the overall productivity and contribute to the success of a project.

Open Source VHDL Verification Methodology (OSVVM) accelerates your FPGA and ASIC verification project by providing utility and model (Verification IP) libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. (see extended abstract for more details)

 


 

Jim Lewis

SynthWorks

Jim Lewis has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.
 

Paul Armijo
GSI Technology

 

George Williams
GSI Technology

 

 

 

AI Journeys to Space

 

 

AI is everywhere. In our phones, in our homes, where we work, where we play. The "new industry revolution" in AI and machine learning, fueled by the "new oil" - massive amounts of data - has spread globally with alarming speed. But, AI has rarely left earth’s orbit, and it’s non-existent in deep space craft. The most recent Mars Rover runs on 15 year old CPU technology. Recently launched spacecraft lack the ability to navigate themselves, requiring constant communication with ground control. Meanwhile, back on earth, humans are already riding in self-driving vehicles, and earthlings routinely run billion-parameter neural networks at real-time speeds.

Disruptive change is on its way, and it's happening at the intersection of space and artificial intelligence. Get ready. AI is soon going where no AI has gone before!

 


 

 

Paul Armijo is the Director of Aerospace & Defense Business Sector at GSI Technology, an embedded hardware and artificial intelligence company. Paul has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community, including roles as the Sr. Director of Systems Development Engineering and Government Programs at Cobham. Prior roles include Advanced Technology Development Manager at General Dynamics, Electrical Systems Lead Engineer on Kepler at Ball Aerospace, Technical Program Manager and Design Lead Engineer on numerous satellite programs at Northrop Grumman Innovation Systems as well as IC Design & Test Engineer at NXP. Paul received his B.S. in Electrical Engineering from Arizona State University.

 

George William is Director of Computing and Data Science at GSI Technology. He's held senior leadership roles in software, data science, and research, including tenures at Apple's New Product Architecture group and at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, software development, cybersecurity, and compute hardware. He is an author on several research papers in computer vision and deep learning, published and presented at NeurIPS, CVPR, ICASSP, SIGGRAPH, Space Computing, and RHET.

 

 

 

 

2020 Exhibit Registration is Open

2020 Exhibitor Floor Plan is available (PDF)

 
 

If you are interested in being a 2020 SEE-MAPLD Exhibitor,
please register or contact us for further information:

Teresa Farris
Archon, LLC
Teresa.Farris@archon-llc.com

Also refer to our Registration page for Exhibitor specific details


Renesas Electronics America Logo


Renesas Electronics America
contact: Oscar Mansilla
phone: 321-724-7247
email: oscar.mansilla.zn@gr.renesas.com
web: www.renesas.com
3D Plus Logo
3D Plus
contact: Timothee Dargnies
phone: 510-824-5591
email: tdargnies@3d-plususa.com
web: www.3d-plus.com
Tortuga Logic Logo


Tortuga Logic
contact: Jennifer Spangle
phone: 888-488-7706
email: jennifer@tortugalogic.com
web: http://www.tortugalogic.com

NASA Electronic Parts and Packaging Program Logo


NASA Electronic Parts and Packaging (NEPP) Program
contact: Jonny Pellish
email: jonathan.pellish@nasa.gov
phone: 301-286-1852
web: nepp.nasa.gov

Radiation Test Solutions Logo
Radiation Test Solutions, Inc.
contact: Malcolm Thomson
email: mthompson@radiationtestsolutions.com
phone: 719-339-3146
web: www.radiationtestsolutions.com

Mentor Logo

Mentor, A Siemens Business
contact: Melissa Ferro
email: melissa_ferro@mentor.com
phone: 510-354-5878
web: www.mentor.com

Integra Logo
Integra Technologies
contact: Ted Barlett
email: ted.barlett@integra-tech.com
phone: 316-630-6801
web: www.integra-tech.com

EMPC Logo

EMPC
contact: Larisa Milic
email: lmilic@empc.com
phone: 301-869-2317
web: www.empc.com

Ultra Tec Logo
ULTRA TEC
contact: Tim Hazeldine
phone: 714-542-0608
email: tim@ultratecusa.com
web: www.ultratecusa.com

4Links Logo
4Links Limited
contact: Dennis Gross
email: dennis@4links.co.uk
phone: +44 7802 385544
web: www.4links.co.uk
Blue Pearl Software Logo
Blue Pearl Software
contact: Jennifer Treiber
email: jenn.treiber@bluepearlsoftware.com
phone: 408-961-0121
web: www.bluepearlsoftware.com

STAR-Dundee Logo
STAR-Dundee
contact: Alberto Gonzalez Villafranca
email: alberto.gonzalez@star-dundee.com
phone: +44 1382 201755
web: www.star-dundee.com

Northwestern Medicine Proton Center Logo
Northwestern Medicine Proton Center
contact: Steve Laub
email: steven.laub@nm.org
phone: 630-821-6376
web: www.protoncenter.nm.org

Cobham Gaisler AB Logo
Cobham
contact: Mia Johansson
email: Mia Johansson
phone: +46 31 7758650
web: www.cobham.com/gaisler


Topline Logo
TopLine
contact: Martin Hart
email: hart@topline.tv
phone: 800-776-9888
web: www.topline.tv
Crocker Nuclear Laboratory, UC Davis Logo
Crocker Nuclear Laboratory, UC Davis
contact: Eric Prebys
email: eprebys@ucdavis.edu
phone: 530-771-7024
web: crocker.ucdavis.edu
Robust Chip Logo
Robust Chip, Inc.
contact: Klas Lilja
phone: 925-425-0820
email: klas.lilja@robustchip.com
web: www.robustchip.com
GSI Technology Logo
GSI Technology
contact: Paul Armijo
phone: 408-331-9863
email: parmijo@gsitechnology.com
web: www.gsitechnology.com

Lattice Semiconductor Logo

Double Exhibit
Lattice Semiconductor

contact: Amy Hill
phone: 408-203-8542
email: amy.hill@latticesemi.com
web: www.latticesemi.com
Oak Ridge National Lab Logo
Oak Ridge National Laboratory Spallation Neutron Source
contact: Bernie Riemer
phone: 865-574-6502
email: riemerbw@ornl.gov
web: neutrons.ornl.gov/sns
SynthWorks Logo
SynthWorks
contact: Jim Lewis
phone: 503-590-4787
email: jim@synthworks.com
web: synthworks.com
 

2020 Workshop Schedule

Sat
Oct 3
Sun
Oct 4
Mon
Oct 5
Tue
Oct 6
Wed
Oct 7
Morning Technical
Sessions
Technical
Sessions
Technical
Sessions
Technical Sessions
Lunch Workshop
Lunch
Workshop
Lunch
Exhibit
Lunch
Exhibit
Lunch
Afternoon Break Exhibit
Setup
Exhibits Poster
Set Up
Evening Welcome
Reception
5:00
Free
Evening
Free
Evening
Exhibit
Reception
Posters and
Reception
5:00 - 9:00

Registration Procedures for the SEE/MAPLD Workshop

Ground Rules For All Attendees
Name badges are required for admittance to the technical sessions, exhibits, and other functions

Registration and badges may not be shared

Badges are ONLY to be used by the person named on the badge
Registration for Attendees and Exhibitors

To register, complete the information and submit payment at:

Attendee and Guest Registration Page

Exhibitor Registration Page

Attendee and Exhibitor registration must be made from these links; checks are not accepted.

For questions, reservation assistance, or to make changes, contact:

Teresa Farris
Teresa.Farris@archon-llc.com
719-964-3617

All meals and evening functions are included in the Attendee registration fee.

Exhibitor-Specific Registration Details

The 2020 SEE/MAPLD Exhibits will open early January. The exhibit cost is $2000 which includes One (1) Complimentary Technical Registration and Two (2) Exhibitor Only badges. Additional Exhibitor Only badges are available for $275.00 and are limited to Three (3) per exhibit.

The six-foot exhibit space includes a six-foot skirted table and two chairs. NOTE: this is a table top only exhibit! There is not room for a 10-foot exhibit booth!

Good news - SEE/MAPLD exhibitors will receive free WiFi in the exhibit area!

Tentative set-up, exhibit hours and tear down are:

Set-up:             Tuesday, Oct 6, 7:15 am - 9:15 am

Exhibit Hours:   Tuesday, Oct 6, 9:30 am - 8:00 pm with morning & afternoon breaks, buffet lunch, evening reception around the exhibit tables
                        Wednesday, Oct 7, 9:30 am - 2:00 pm with a morning break and buffet, with exhibitor raffles, around the exhibit tables

Tear down:       Wednesday, Oct 7, after 2:00 pm

Guest Registration


New for 2020: SEE/MAPLD now offers a Guest Badge that allows companions to attend all of the reception functions.

2020 SEE/MAPLD Fees

SEE/MAPLD Technical Registration includes 3 1/2 days of
Technical Sessions, Tutorials and Invited Speakers

Breakfast, lunch and breaks are provided Oct 4-7, 2020

Saturday, October 3rd: Welcome Reception
Tuesday, October 6th: Exhibitor Reception
Wednesday, October 7th: Poster Reception

  Early Late (After Tuesday, September 1)
Attendee $775 $825
Student $375 $425
Exhibitor $2000


Registered Attendees may purchase guest badges.

The guest badge provides access to the Welcome Reception,
Exhibitor Reception and Poster Reception.

Guest Badge $125


Official SEE/MAPLD Registration Cancellation Policy (Technical and Exhibits)

Registration cancellations must be requested by September 1, 2020. Please email
Teresa.Farris@archon-llc.com with your request. A $50 processing fee will be withheld from all refunds.

Due to advance financial commitments, refunds of conference registration fees requested
after September 1, 2020, cannot be guaranteed. Consideration of requests for refunds
will be processed after the conference on a case-by-case basis

Hotel Reservation


Please refer to our Hotel Information page to reserve your room for SEE/MAPLD

SEE/MAPLD begins Saturday, October 3 with a 5:00 pm Welcome Reception and
ends Wednesday, October 7 with a 5:00-9:00 pm Poster Session & Reception
Please make your hotel reservations accordingly!

Sat
Oct 3
Sun
Oct 4
Mon
Oct 5
Tue
Oct 6
Wed
Oct 7
Morning Technical
Sessions
Technical
Sessions
Technical
Sessions
Technical Sessions
Lunch Workshop
Lunch
Workshop
Lunch
Exhibit
Lunch
Exhibit
Lunch
Afternoon Break Exhibit
Setup
Exhibits Poster
Set Up
Evening Welcome
Reception
5:00
Free
Evening
Free
Evening
Exhibit
Reception
Posters and
Reception
5:00 - 9:00

2020 Hotel Reservations for the La Jolla Marriott at the SEE-MAPLD

SEE/MAPLD has a hotel block of rooms at the La Jolla Marriott. The rate is the Government Per Diem of $173.00 plus sales tax with
reduced parking rate of $12.00 for attendees registered at the hotel. The block opens May 7th and closes on September 11, 2020.
SEE/MAPLD appreciates your patronage at the La Jolla Marriott.

Please reserve your room by following the link below. The rate will remain $173!
Book your group rate for 2020 SEE/MAPLD Conference October 4-7 

Parking for workshop attendees is at special discount rate of $12/day

Room block beginning and end dates: 9/29/20 - 10/10/20
Last day to book: Friday, September 11th, 2020



Local visitor information for La Jolla, CA and the San Diego area.

The meeting is being held near the University Town Center (UTC)/Golden Triangle in La Jolla, CA.
This is about a 10 minute drive from the ocean and downtown La Jolla.

Marriott LaJolla local Arrangement and Transportation Information

There are many fine local restaurants and accessible shopping within walking distance of the hotel.
Several useful websites that may be of interest are:

http://www.sandiego.org/discover/la-jolla.aspx
http://www.dreamlajolla.com
http://www.maintour.com/socal/sdg_utc.htm
http://www.lajollabythesea.com

And for the bargain hunters:
http://www.halfpricesandiego.com

Previous SEE Symposium and SEE/MAPLD Home Pages: 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019

SEE Symposium and SEE/MAPLD Presentation Materials 2006-2019

Contact Us

General Chair(s): SEE: David Hansen, Data Device Corporation / MAPLD: Gregory Allen, NASA/JPL-Caltech
Technical Program Chair(s): SEE: Megan Casey, NASA Goddard Space Flight Center / MAPLD Co-Chairs: Nadia Rezzak, Microchip Technology, Inc. and Pierre Maillard, Xilinx
Poster Session Chair: Martha O'Bryan, SSAI / NASA Goddard Space Flight Center
Industrial Exhibit Chairwoman: Teresa Farris, Archon, LLC
Local Arrangements & Registration Services: Teresa Farris, Archon, LLC
Website Curator: Carl Szabo, SSAI / NASA Goddard Space Flight Center

SEE/MAPLD Code of Conduct

Subscribe (Opt-In) to our email list (Provided by NASA/NEPP)