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29th Annual

Single Event Effects (SEE) Symposium coupled with the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop

May 18 - 21, 2020

San Diego, Marriott La Jolla

Tutorial Speakers Announced

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Now featuring over 700 talks spanning years 2006-2019
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Please join us for the jointly held

2020 Single Event Effects (SEE) Symposium and Military and Aerospace
Programmable Logic Devices (MAPLD) Workshop

May 18 - 21, 2020

at the

Marriott LaJolla, CA, USA

Abstract submission is now closed

Click Here for Registration Details

We are seeking contributions in the following areas, but all submissions will be reviewed. Four sessions are available: SEE, MAPLD, Combined, and Poster. The Combined Session includes submissions that cross SEE and MAPLD themes. The Poster Session can include SEE, MAPLD, or Combined content. Please refrain from technical content reasonably classified as product marketing.

SEE Symposium MAPLD
New! Artificial Intelligence (AI) / Machine Learning (ML) in FPGAs/SoCs: AI / ML design considerations for reliable terrestrial, avionic, and aerospace applications; using AI for SEE mitigation; SEE evaluation of designs leveraging AI / ML
Phenomena: Upsets, Functional Interrupts, Transients, Latchup, Gate Rupture, Burnout, etc. FPGAs/SoCs, PLDs, and New Devices: New and/or novel FPGA and PLDs; Benchmarking of FPGAs and PLDs; Applications of space-borne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Charge Transport and Collection, Impact of Circuit and Environmental Parameters, etc. Mitigation of Single event effects in FPGAs/SoCs, PLDs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), upset mitigation techniques and automated tools, etc.
SEE Mitigation Methods Including Radiation Hardened by Design (RHBD) and by Process (RHBP): Approaches for gaining SEE hardness in commercial devices, etc. Designing with FPGAs/SoCs, and PLDs: agile methods, ESL/HLS and model-based engineering techniques, embedded processing, and synthesis efficiency improvements.
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Pulsed Laser Test Facilities. Validation and Verification of FPGAs/SoCs, and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices from LEO to Interplanetary, High Altitude Aircraft, and Terrestrial. Availability/Reliability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data and Measurement Techniques: Memories, Analog/Digital Circuits, systems-on-chip (SoCs), Field Programmable Gate Arrays (FPGAs), Optocouplers, Photonic Integrated Circuits, Power Converters, Sensors, etc. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, etc.
Systems and Error Rate Computation: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems; Analytic, Monte Carlo, Mixed-Level, methods, etc. Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Education: Education Practices, Market Demands for Military and Aerospace Component Engineers, and Engineer Retention.
*All options subject to change any time, per the discretion of the conference committee

The 2020 Preliminary Program will become available after abstract submission and review has completed

2020 SEE/MAPLD is pleased to announce the following tutorial sessions and speakers:



Fault-tolerance Concepts, Single Event Effects
Characterization, FPGA Scrubbing, and
Other Use Cases Using Industry Product Examples


This tutorial will focus on fault-tolerance concepts to allow uninterrupted software execution in the presence of correctable errors and SEE characterization results with the GR740 SoC and GR716 Microcontroller as product examples. The tutorial will also cover the development of the GRSCRUB FPGA scrubber IP core and its planned inclusion in the GR716 flight models.


Lucas Tambara

Cobham Gaisler

Lucas Antunes Tambara is a Component Engineer at Cobham Gaisler, Gothenburg, Sweden. He received his Ph.D. in Microelectronics and M.Sc. in Electrical Engineering from Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. He received his B.Sc. in Computer Science from Universidade Federal de Santa Maria (UFSM), Santa Maria, Brazil. His interests include radiation effects on integrated circuits, fault tolerance, embedded systems, and hardware design. Lucas has authored several publications in IEEE transactions and conferences, and also serves in the reviewer board of several international journals and frequently in the technical program committee for the RADECS and NSREC conferences.



Better FPGA Verification with Open Source
VHDL Verification Methodology (OSVVM)


Verification consumes a considerable amount of the FPGA development cycle. Using an effective verification methodology is important as it can improve the overall productivity and contribute to the success of a project.

Open Source VHDL Verification Methodology (OSVVM) accelerates your FPGA and ASIC verification project by providing utility and model (Verification IP) libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. (see extended abstract for more details)



Jim Lewis


Jim Lewis has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.

Paul Armijo
GSI Technology


George Williams
GSI Technology




AI Journeys to Space



AI is everywhere. In our phones, in our homes, where we work, where we play. The "new industry revolution" in AI and machine learning, fueled by the "new oil" - massive amounts of data - has spread globally with alarming speed. But, AI has rarely left earth’s orbit, and it’s non-existent in deep space craft. The most recent Mars Rover runs on 15 year old CPU technology. Recently launched spacecraft lack the ability to navigate themselves, requiring constant communication with ground control. Meanwhile, back on earth, humans are already riding in self-driving vehicles, and earthlings routinely run billion-parameter neural networks at real-time speeds.

Disruptive change is on its way, and it's happening at the intersection of space and artificial intelligence. Get ready. AI is soon going where no AI has gone before!




Paul Armijo is the Director of Aerospace & Defense Business Sector at GSI Technology, an embedded hardware and artificial intelligence company. Paul has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community, including roles as the Sr. Director of Systems Development Engineering and Government Programs at Cobham. Prior roles include Advanced Technology Development Manager at General Dynamics, Electrical Systems Lead Engineer on Kepler at Ball Aerospace, Technical Program Manager and Design Lead Engineer on numerous satellite programs at Northrop Grumman Innovation Systems as well as IC Design & Test Engineer at NXP. Paul received his B.S. in Electrical Engineering from Arizona State University.


George William is Director of Computing and Data Science at GSI Technology. He's held senior leadership roles in software, data science, and research, including tenures at Apple's New Product Architecture group and at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, software development, cybersecurity, and compute hardware. He is an author on several research papers in computer vision and deep learning, published and presented at NeurIPS, CVPR, ICASSP, SIGGRAPH, Space Computing, and RHET.





2020 Exhibit Registration Is Open!

2020 Exhibitor Floor Plan is available (PDF)


If you are interested in being a 2020 SEE-MAPLD Exhibitor,
please register or contact us for further information:

Teresa Farris
Archon, LLC

Also refer to our Registration page for Exhibitor specific details

Renesas Electronics America Logo

Renesas Electronics America
contact: Oscar Mansilla
phone: 321-724-7247
3D Plus Logo
3D Plus
contact: Timothee Dargnies
phone: 510-824-5591
Microchip Technology, Inc. Logo
Microchip Technology, Inc.
contact: Megan Walton
phone: 949-356-1046
Tortuga Logic Logo

Tortuga Logic
contact: Jennifer Spangle
phone: 888-488-7706

NASA Electronic Parts and Packaging Program Logo

NASA Electronic Parts and Packaging (NEPP) Program
contact: Jonny Pellish
phone: 301-286-1852

Radiation Test Solutions Logo
Radiation Test Solutions, Inc.
contact: Malcolm Thomson
phone: 719-339-3146

Mentor Logo

Mentor, A Siemens Business
contact: Melissa Ferro
phone: 510-354-5878

Integra Logo
Integra Technologies
contact: Ted Barlett
phone: 316-630-6801


contact: Larisa Milic
phone: 301-869-2317

Ultra Tec Logo
contact: Tim Hazeldine
phone: 714-542-0608

4Links Logo
4Links Limited
contact: Dennis Gross
phone: +44 7802 385544
Blue Pearl Software Logo
Blue Pearl Software
contact: Jennifer Treiber
phone: 408-961-0121

STAR-Dundee Logo
contact: Alberto Gonzalez Villafranca
phone: +44 1382 201755

Northwestern Medicine Proton Center Logo
Northwestern Medicine Proton Center
contact: Steve Laub
phone: 630-821-6376

Cobham Gaisler AB Logo
contact: Mia Johansson
email: Mia Johansson
phone: +46 31 7758650

Topline Logo
contact: Martin Hart
phone: 800-776-9888
Crocker Nuclear Laboratory, UC Davis Logo
Crocker Nuclear Laboratory, UC Davis
contact: Eric Prebys
phone: 530-771-7024
Robust Chip Logo
Robust Chip, Inc.
contact: Klas Lilja
phone: 925-425-0820
GSI Technology Logo
GSI Technology
contact: Paul Armijo
phone: 408-331-9863
Lattice Semiconductor Logo
Lattice Semiconductor
contact: Amy Hill
phone: 408-203-8542
Oak Ridge National Lab Logo
Oak Ridge National Laboratory Spallation Neutron Source
contact: Bernie Riemer
phone: 865-574-6502
  SynthWorks Logo
contact: Jim Lewis
phone: 503-590-4787

Registration Procedures for the SEE/MAPLD Workshop

Ground Rules For All Attendees
Name badges are required for admittance to the technical sessions, exhibits, and other functions

Registration and badges may not be shared

Badges are ONLY to be used by the person named on the badge
Registration for Attendees and Exhibitors

To register, complete the information and submit payment at:

Attendee and Guest Registration Page

Exhibitor Registration Page

Attendee and Exhibitor registration must be made from these links; checks are not accepted.

For questions, reservation assistance, or to make changes, contact:

Teresa Farris

All meals and evening functions are included in the Attendee registration fee.

Exhibitor-Specific Registration Details

The 2020 SEE/MAPLD Exhibits will open early January. The exhibit cost is $2000 which includes One (1) Complimentary Technical Registration and Two (2) Exhibitor Only badges. Additional Exhibitor Only badges are available for $275.00 and are limited to Three (3) per exhibit.

The six-foot exhibit space includes a six-foot skirted table and two chairs. NOTE: this is a table top only exhibit! There is not room for a 10-foot exhibit booth!

Good news - SEE/MAPLD exhibitors will receive free WiFi in the exhibit area!

Tentative set-up, exhibit hours and tear down are:

Set-up:             Tuesday, May 19, 7:15 am - 9:15 am
Exhibit Hours:   Tuesday, May 19, 9:30 am - 8:00 pm with morning and afternoon breaks, a buffet lunch, and an evening reception around the exhibit tables
                        Wednesday, May 20, 9:30 am - 2:00 pm with a morning break and buffet, with exhibitor raffles, around the exhibit tables
Tear down:       Wednesday, May 20 after 2:00 pm

Guest Registration

New for 2020: SEE/MAPLD now offers a Guest Badge that allows companions to attend all of the reception functions.

2020 SEE/MAPLD Fees

SEE/MAPLD Technical Registration includes 3 1/2 days of
Technical Sessions, Tutorials and Invited Speakers

Breakfast, lunch and breaks are provided May 18-21, 2020

Sunday, May 17th: Registration Reception
Tuesday, May 19th: Exhibitor Reception
Wednesday, May 20th: Poster Reception

  Early Late (After Friday, April 17)
Attendee $775 $825
Student $375 $425
Exhibitor $2000

Registered Attendees may purchase guest badges.

The guest badge provides access to the Registration Reception,
Exhibitor Reception and Poster Reception.

Guest Badge $125

Official SEE/MAPLD Registration Cancellation Policy (Technical and Exhibits)

Registration cancellations must be requested by May 8, 2020. Please email with your request. A $50 processing fee will be withheld from all refunds.

Due to advance financial commitments, refunds of conference registration fees requested
after May 8, 2020, cannot be guaranteed. Consideration of requests for refunds
will be processed after the conference on a case-by-case basis

Hotel Reservation

Please refer to our Hotel Information page to reserve your room for SEE/MAPLD

2020 Hotel Reservations for the La Jolla Marriott at the SEE-MAPLD

SEE/MAPLD has a hotel block of rooms at the La Jolla Marriott. The rate is the Government Per Diem of $173.00 plus sales tax with
reduced parking rate of $12.00 for attendees registered at the hotel. The block is open now and closes on May 8, 2020.
SEE/MAPLD appreciates your patronage at the La Jolla Marriott.

Book your group rate for 2020 SEE/MAPLD Conference May 18-21 
Note: Parking for workshop attendees is at special discount rate of $12/day

Room block beginning and end dates: 5/13/20 - 5/24/20
Last day to book: Friday, May 8th, 2020

Local visitor information for La Jolla, CA and the San Diego area.

The meeting is being held near the University Town Center (UTC)/Golden Triangle in La Jolla, CA.
This is about a 10 minute drive from the ocean and downtown La Jolla.

Marriott LaJolla local Arrangement and Transportation Information

There are many fine local restaurants and accessible shopping within walking distance of the hotel.
Several useful websites that may be of interest are:

And for the bargain hunters:

Previous SEE Symposium and SEE/MAPLD Home Pages: 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019

SEE Symposium and SEE/MAPLD Presentation Materials 2006-2019

Contact Us

General Chair(s): SEE: David Hansen, Data Device Corporation / MAPLD: Gregory Allen, NASA/JPL-Caltech
Technical Program Chair(s): SEE: Megan Casey, NASA Goddard Space Flight Center / MAPLD Co-Chairs: Nadia Rezzak, Microchip Technology, Inc. and Pierre Maillard, Xilinx
Poster Session Chair: Martha O'Bryan, SSAI / NASA Goddard Space Flight Center
Industrial Exhibit Chairwoman: Teresa Farris, Archon, LLC
Local Arrangements & Registration Services: Teresa Farris, Archon, LLC
Website Curator: Carl Szabo, SSAI / NASA Goddard Space Flight Center

SEE/MAPLD Code of Conduct

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