SEE/MAPLD Workshop Banner

Due to COVID-19 concerns, SEE/MAPLD is going virtual for 2020.

Welcome to the homepage of the 29th Annual Single Event Effects (SEE) Symposium
coupled with the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop

SEE/MAPLD's Virtual Event will take place October 6-8, 2020,
with oral, poster, tutorial sessions, including Live Q&A, and Exhibits.

Virtual content will be available until December 31, 2020 for all Registrants.
Registration fees are the same from October 6 to December 31, 2020;
no refunds will be offered.


The Final Technical Program has been posted

Registration for our Virtual Event is open!


Learn about our 2020 Invited Tutorial Speakers


Our Presentation Archive has been updated!
Now featuring over 700 talks spanning years 2006-2019
Jump to the Archives


SEE/MAPLD Needs Your Help
Sign up / encourage others to join our official email list for workshop announcements
(Opt-In; Managed by NASA/NEPP for Conference and Workshop Outreach)


Please join us for the jointly held, 100% virtual

2020 Single Event Effects (SEE) Symposium and Military and Aerospace
Programmable Logic Devices (MAPLD) Workshop


Virtual Meeting Dates: October 6 - 8, 2020


Click Here for Registration Details


We are seeking contributions in the following areas, but all submissions will be reviewed. Four sessions are available: SEE, MAPLD, Combined, and Poster. The Combined Session includes submissions that cross SEE and MAPLD themes. The Poster Session can include SEE, MAPLD, or Combined content. Please refrain from technical content reasonably classified as product marketing.

SEE Symposium MAPLD
New! Artificial Intelligence (AI) / Machine Learning (ML) in FPGAs/SoCs: AI / ML design considerations for reliable terrestrial, avionic, and aerospace applications; using AI for SEE mitigation; SEE evaluation of designs leveraging AI / ML
Phenomena: Upsets, Functional Interrupts, Transients, Latchup, Gate Rupture, Burnout, etc. FPGAs/SoCs, PLDs, and New Devices: New and/or novel FPGA and PLDs; Benchmarking of FPGAs and PLDs; Applications of space-borne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Charge Transport and Collection, Impact of Circuit and Environmental Parameters, etc. Mitigation of Single event effects in FPGAs/SoCs, PLDs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), upset mitigation techniques and automated tools, etc.
SEE Mitigation Methods Including Radiation Hardened by Design (RHBD) and by Process (RHBP): Approaches for gaining SEE hardness in commercial devices, etc. Designing with FPGAs/SoCs, and PLDs: agile methods, ESL/HLS and model-based engineering techniques, embedded processing, and synthesis efficiency improvements.
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Pulsed Laser Test Facilities. Validation and Verification of FPGAs/SoCs, and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices from LEO to Interplanetary, High Altitude Aircraft, and Terrestrial. Availability/Reliability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data and Measurement Techniques: Memories, Analog/Digital Circuits, systems-on-chip (SoCs), Field Programmable Gate Arrays (FPGAs), Optocouplers, Photonic Integrated Circuits, Power Converters, Sensors, etc. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, etc.
Systems and Error Rate Computation: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems; Analytic, Monte Carlo, Mixed-Level, methods, etc. Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Education: Education Practices, Market Demands for Military and Aerospace Component Engineers, and Engineer Retention.
*All options subject to change any time, per the discretion of the conference committee

 

2020 SEE/MAPLD Combined Workshop Final Program
Click Here for PDF Copy

Important Note to All Attendees:

Presentations in each session will play in a non-stop fashion, followed by live Q&A

If a session concludes earlier than anticipated, the following session(s) will remain at their scheduled time(s)

 

Tuesday, October 6
PDT
EDT
Paris
Session
Presentation / Speaker
6:30 AM
9:30 AM
3:30 PM
Exhibitor Breakfast - EPC SPACE
6:45 AM
9:45 AM
3:45 PM
7:00 AM
10:00 AM
4:00 PM
Opening Remarks - David Hansen, Single Event Effects (SEE) General Chair
SEE Track Introduction - Megan Casey, SEE Technical Chair
7:15 AM
10:15 AM
4:15 PM
Facilities
SEEMS - A New Facility for Single Event Effects Testing and Muon Spectroscopy
Bernard Riemer, Oak Ridge National Laboratory
7:30 AM
10:30 AM
4:30 PM
The LANSCE Facility for Measurement of Neutron-induced Failure in Semiconductor Devices
Stephen Wender, Los Alamos National Laboratory
7:45 AM
10:45 AM
4:45 PM
Radiation Effects Facility at Crocker Nuclear Laboratory
Eric Prebys, University of CA Davis, Crocer Nuclear Laboratory
8:00 AM
11:00 AM
5:00 PM
Domestic Heavy Ion Single-Event Effects Test Facilities: Needs, Current Status, and Future
Jonathan Pellish, NASA Goddard Space Flight Center
8:15 AM
11:15 AM
5:15 PM
Heavy Ion Beams from the K150 Cyclotron at TAMU
Henry Clark, Cyclotron Institute at Texas A&M University
8:30 AM
11:30 AM
5:30 PM
Live Q&A for Facilities Session Speakers
Moderated by: Megan Casey
8:45 AM
11:45 AM
5:45 PM
Exhibitor Break - STAR DUNDEE
9:00 AM
12:00 PM
6:00 PM
9:15 AM
12:15 PM
6:15 PM
Invited Tutorial #1

Artificial Intelligence (AI) Journeys to Space

Paul Armijo and George Williams, GSI Technology

(40 Minute Duration, 5 Minute Q&A Moderated by Megan Casey)

9:30 AM
12:30 PM
6:30 PM
9:45 AM
12:45 PM
6:45 PM
10:00 AM
1:00 PM
7:00 PM
Exhibitor Break - MENTOR, A SIEMENS BUSINESS
10:15 AM
1:15 PM
7:15 PM
10:30 AM
1:30 PM
7:30 PM
Military and Aerospace Programmable Logic Devices (MAPLD) Opening Remarks - Gregory Allen, MAPLD General Chair
MAPLD Track Introduction - Nadia Rezzak / Pierre Maillard, MAPLD Technical Chairs
10:45 AM
1:45 PM
7:45 PM
FPGAs / SoCs, PLDs, and New Devices
Heavy Ion and Proton Induced Single Event Effects on Microchip RT PolarFire FPGA
Nadia Rezzak, Microchip Technology, Inc.
11:00 AM
2:00 PM
8:00 PM
Architecture and Radiation Advantage of Advanced FD-SOI FPGAs
Melanie Berg, Space R2, LLC. / Lattice Semiconductor
11:15 AM
2:15 PM
8:15 PM
Still Latched-up After All These Years: More Clues in the 7-Series FPGA Micro-Latchup Mystery
Gary Swift, Swift Engineering & Radiation Services, LLC.
11:30 AM
2:30 PM
8:30 PM
Live Q&A for FPGAs / SoCs, PLDs, and New Devices Session Speakers
Moderated by: Nadia Rezzak, Pierre Maillard
11:45 AM
2:45 PM
8:45 PM
Exhibitor Break - INTEGRA TECH
12:00 PM
3:00 PM
9:00 PM
12:15 PM
3:15 PM
9:15 PM

Panel Discussion:

Supply Chain Risk Management

Panelist 1:
Paul Quintana, Microchip Technology, Inc.
12:30 PM
3:30 PM
9:30 PM
Panelist 2 (Live):
John Latimer, Xilinx, Inc.
12:45 PM
3:45 PM
9:45 PM
Live Q&A
Moderated by: Nadia Rezzak, Pierre Maillard
1:00 PM
4:00 PM
10:00 PM
Mitigation of Single Event Effects in FPGAs/SoCs, PLDs and Commercial Electronics
Fault Injection to Verify Functional Safety Logic
Joe Mallett, Synopsys
1:15 PM
4:15 PM
10:15 PM
Rethinking Your Approach to Radiation Mitigation
Jacob Wiltgen, Mentor - A Siemens Business
1:30 PM
4:30 PM
10:30 PM
Implementing Temporal Mitigation Solutions in FPGAs
Kamesh Ramani, Mentor - A Siemens Business
1:45 PM
4:45 PM
10:45 PM
SpaceFibre for FPGA: IPs and RTG4 Radiation Test Results
Alberto Gonzalez, STAR-Dundee, Ltd.
2:00 PM
5:00 PM
11:00 PM
Live Q&A for Mitigation of Single Event Effects in FPGAs/SoCs, PLDs and Commercial Electronics Session
Moderated by: Nadia Rezzak, Pierre Maillard
2:15 PM
5:15 PM
11:15 PM

Exhibitor Reception

All attendees are invited to join us and welcome all of our 2020 Supporters and Exhibitors!

Technical / Social Meeting Rooms Provided:
Collaboration Corner
SEE Beam-Off
Design This / Verify That
Students and Young Professionals Lounge
Combo Special

2:30 PM
5:30 PM
11:30 PM
2:45 PM
5:45 PM
11:45 PM
3:00 PM
6:00 PM
12:00 AM
3:15 PM
6:15 PM
12:15 AM
3:30 PM
6:30 PM
12:30 AM
3:45 PM
6:45 PM
12:45 AM
End of Tuesday Workshop Events


Wednesday, October 7
PDT
EDT
Paris
Session
Presentation / Speaker
6:30 AM
9:30 AM
3:30 PM
Exhibitor Breakfast - ASAP-1 ULTRA TEC
6:45 AM
9:45 AM
3:45 PM
7:00 AM
10:00 AM
4:00 PM
7:15 AM
10:15 AM
4:15 PM
Systems and Error Rate Computation
Discrete Binning Analysis of Single Event Transient Pulse Width for Rate Calculations
Michael Campola, NASA Goddard Space Flight Center
7:30 AM
10:30 AM
4:30 PM
The Radiation Assessment Matrix (RAM): A Systematic Approach to SEE Circuit Analysis in Support of Single-Event Effects Criticality Assessment (SEECA)
Razvan Gaza, NASA Johnson Space Center
7:45 AM
10:45 AM
4:45 PM
Low and Medium Earth-Orbit Rates Using Design-of-Experiments and Monte-Carlo Methods
David Hansen, Data Device Corporation
8:00 AM
11:00 AM
5:00 PM
A Track-Structure Based Approach to Upset-Rate Calculations
David Hansen, Data Device Corporation
8:15 AM
11:15 AM
5:15 PM
Single-Event Effects Criticality Assessment (SEECA) Guidance for Implementation
Michael Campola, NASA Goddard Space Flight Center
8:30 AM
11:30 AM
5:30 PM
Recent Results and Current Status of the Quasi-Bessel Beam Approach for Pulsed-Laser SEE Studies
Joel Hales, U.S. Naval Research Laboratory
8:45 AM
11:45 AM
5:45 PM
Error Rate Calculation of Functional Failures Induced by Single-Event Transients in Clock Distribution Networks
Thomas Lange, iRoC Technologies / Politecnico di Torino
9:00 AM
12:00 PM
6:00 PM
Live Q&A for Systems and Error Rate Computation Session Speakers
Moderated by: Megan Casey
9:15 AM
12:15 PM
6:15 PM
Exhibitor Break - EMPC
9:30 AM
12:30 PM
6:30 PM
9:45 AM
12:45 PM
6:45 PM
Data Analysis
Analysis of Single Event Transients (SETs) using Machine Learning and Ionizing Radiation Effects Spectroscopy (IRES)
Daniel Loveless, University of Tennessee - Chattanooga
10:00 AM
1:00 PM
7:00 PM
Novel Approach to Modeling and Prediction of Single Event Upsets at Component Level
Ashok Alagappan, ANSYS
10:15 AM
1:15 PM
7:15 PM
Data: What Are They Good For? (Absolutely...)
Ray Ladbury, NASA Goddard Space Flight Center
10:30 AM
1:30 PM
7:30 PM
Live Q&A for Data Analysis Session Speakers
Moderated by: Megan Casey
10:45 AM
1:45 PM
7:45 PM
Exhibitor Break - RADIATION TEST SOLUTIONS
11:00 AM
2:00 PM
8:00 PM
11:15 AM
2:15 PM
8:15 PM
Invited Tutorial #2

Better FPGA Verification with Open Source VHDL Verification Methodology (OSVVM)

Jim Lewis, SynthWorks

(40 Minute Duration, 5 Minute Q&A Moderated by Nadia Rezzak and Pierre Maillard)

11:30 AM
2:30 PM
8:30 PM
11:45 AM
2:45 PM
8:45 PM
12:00 PM
3:00 PM
9:00 PM
Exhibitor Break - COBHAM SEMICONDUCTOR AND SPACE SOLUTIONS
12:15 PM
3:15 PM
9:15 PM
12:30 PM
3:30 PM
9:30 PM
Validation and Verification of
FPGAs / SoCs and PLDs
Using Fault Injection to Predict the Error Rate of a Large Complex Design in a Non-Hardened SRAM-Based Xilinx 7-Series FPGA
Patrick Fleming, Raytheon Space and Airborne Systems
12:45 PM
3:45 PM
9:45 PM
Fault Tracking and Modeling in Advanced Node Processors of Single Event Effects
Matthew Cannon, Sandia National Laboratories
1:00 PM
4:00 PM
10:00 PM
PMPedia (Parts, Materials, and Processes) Encyclopedia: A Crowd-Sourced Space Radiation Electronics Knowledge Repository
Allyson Yarbrough, The Aerospace Corporation
1:15 PM
4:15 PM
10:15 PM
Accelerating and Improving Design Reviews with Analysis Tools
Jason Riddley, NASA Jet Propulsion Laboratory
1:30 PM
4:30 PM
10:30 PM
Executable Specifications for Hardware Assurance of SoCs and FPGAs
Alric Althoff, Tortuga Logic
1:45 PM
4:45 PM
10:45 PM
Using Static RTL Analysis to Accelerate Satellite FPGA Verification (Live)
Scott Calkins, Blue Pearl Software
2:00 PM
5:00 PM
11:00 PM
Live Q&A for Validation and Verification of FPGAs / SoCs and PLDs Session Speakers
Moderated by: Nadia Rezzak, Pierre Maillard
2:15 PM
5:15 PM
11:15 PM
Poster Session

All Posters Visible & Interactive Throughout Entire Session

SEE Testing of Renesas Intersil Current Sense Amplifier
Kiran Bernard, Renesas Electronics America, Inc.

Protons, Protons Everywhere - But Where Do We Test in the U.S.?
Kenneth LaBel, Science Systems and Applications, Inc. / GSFC

Single Event Effects Characterization of Microchip Programmable Current Limiting Power Switch LX7712
Marco Leuenberger, Microchip Technology

Technology Evaluation for High Voltage Space Applications
Matt Von Thun, Cobham Advanced Electronic Solutions

Reconfigurable Image Processing Applications on FPGAs
Mohamed El-Hadedy, California Polytechnic University

Scrubbing and In-Orbit Re-Configuration Options for Ultra Deep Sub-Micron Space-Grade FPGAs
Rajan Bedi, Space Chips, LLC.

2:30 PM
5:30 PM
11:30 PM
2:45 PM
5:45 PM
11:45 PM
3:00 PM
6:00 PM
12:00 AM
3:15 PM
6:15 PM
12:15 AM
3:30 PM
6:30 PM
12:30 AM
3:45 PM
6:45 PM
12:45 AM
End of Wednesday Workshop Events


Thursday, October 8
PDT
EDT
Paris
Session
Presentation / Speaker
6:30 AM
9:30 AM
3:30 PM
Exhibitor Breakfast - EPC SPACE
6:45 AM
9:45 AM
3:45 PM
7:00 AM
10:00 AM
4:00 PM
7:15 AM
10:15 AM
4:15 PM
Invited Tutorial #3

Fault-tolerance Concepts, Single Event Effects Characterization, FPGA Scrubbing, and Other Use Cases Using Industry Product Examples

Lucas Tambara, Cobham Gaisler

(40 Minute Duration, 5 Minute Q&A Moderated by Nadia Rezzak and Pierre Maillard)

7:30 AM
10:30 AM
4:30 PM
7:45 AM
10:45 AM
4:45 PM
8:00 AM
11:00 AM
5:00 PM
Exhibitor Break - NORTHWESTERN MEDICINE PROTON CENTER
8:15 AM
11:15 AM
5:15 PM
8:30 AM
11:30 AM
5:30 PM
Devices
NVIDIA Jetson TX2i Radiation Report
Christopher Heistand, Johns Hopkins Applied Physics Laboratory
8:45 AM
11:45 AM
5:45 PM
Electrical Measurement of Cell-to-Cell Variation of Critical Charge in SRAM and Sensitivity to Single-Event Upsets by Low-Energy Protons
James Cannon, University of Tennessee - Chattanooga
9:00 AM
12:00 PM
6:00 PM
Stuck Bits from Co-60, Electrons, Protons, and Heavy Ions
Steven Guertin, NASA Jet Propulsion Laboratory
9:15 AM
12:15 PM
6:15 PM
Live Q&A for Devices Session Speakers
Moderated by: Megan Casey
9:30 AM
12:30 PM
6:30 PM
Exhibitor Break - NASA ELECTRONIC PARTS AND PACKAGING (NEPP) PROGRAM
9:45 AM
12:45 PM
6:45 PM
10:00 AM
1:00 PM
7:00 PM
Designing with FPGAs / SoCs and PLDs
Performance Evaluation of Wide-range of AI Applications on Rasberry Pi
Mohamed El-Hadedy, California Polytechnic University
10:15 AM
1:15 PM
7:15 PM
Development and FPGA Roadmap for LEON5FT and NOEL-V Processor Models
Jan Andersson, Cobham Gaisler
10:30 AM
1:30 PM
7:30 PM
The Power of Dense Silicon: Trending Features and Support at Chip-Level Enabling New Levels of Integration and Dependability for Avionics Systems
Jyotika Athavale, Intel Corporation
10:45 AM
1:45 PM
7:45 PM
Towards the Use of Machine Learning to Estimate the Functional Failure Rate of Complex Circuits
Thomas Lange, iRoC Technologies / Politecnico di Torino
11:00 AM
2:00 PM
8:00 PM
Live Q&A for Designing with FPGAs / SoCs and PLDs Session Speakers
Moderated by: Nadia Rezzak, Pierre Maillard
11:15 AM
2:15 PM
8:15 PM
Exhibits Open

Exhibitor Webinars / Demos
All Exhibits to open at 11:15 AM PDT

Exhibitor Webinars and Demos begin at 11:30 AM PDT
Visit Exhibitor Booths for details and access information

11:30 AM
2:30 PM
8:30 PM

Demo of GRSCRUB scrubber with UltraScale FPGA and Space-Grade Processor Overview/Roadmap

Cobham Gaisler

Proton Testing at the Northwestern Medicine Proton Center: Everything You Need to Know

Northwestern Medicine Proton Center

Very High Speed SpaceFibre Interfacing and Analysis with the STAR-Ultra PCIe

STAR-Dundee

Rad Hard Power Solution for the XQRKU060

Renesas

3D Plus New Product Overview

3D Plus

Radiation Transport and Effects Using NOVICE

EMPC

Single Event Effect Testing using a near-IR Laser System

Allied Scientific Pro

SEEMS - Neutrons and Protons for Electronics SEE Testing

Oak Ridge National Laboratory

Radiation Hard Standard Cell Libraries in Advanced FinFET Technology

Robust Chip

AI's Journey To Space

GSI Technology

RadHard Precision and Digital Timescale

Silicon Technologies

Tales From the Trenches: A Security Engineer's Perspective on SoC Weaknesses

Tortuga Logic

Demo of Open Source VHDL Verification Methodology

SynthWorks

An Alternative Approach to SEE Testing of GaN HEMTs

EPC Space

eFPGA, What's Available Now, What's Coming and What's Possible!

FlexLogix

Is Your 'Safe' FPGA Design Safe Enough?

Mentor, A Siemens Business

11:45 AM
2:45 PM
8:45 PM
12:00 PM
3:00 PM
9:00 PM
12:15 PM
3:15 PM
9:15 PM
12:30 PM
3:30 PM
9:30 PM
12:45 PM
3:45 PM
9:45 PM
1:00 PM
4:00 PM
10:00 PM
1:15 PM
4:15 PM
10:15 PM
1:30 PM
4:30 PM
10:30 PM
1:45 PM
4:45 PM
10:45 PM
2:00 PM
5:00 PM
11:00 PM
2:15 PM
5:15 PM
11:15 PM
2:30 PM
5:30 PM
11:30 PM
2:45 PM
5:45 PM
11:45 PM
3:00 PM
6:00 PM
12:00 AM
3:15 PM
6:15 PM
12:15 AM
3:30 PM
6:30 PM
12:30 AM
End of Thursday Workshop Events

2020 SEE/MAPLD is pleased to announce the following Invited Tutorial Sessions and Speakers:


 

 

Fault-tolerance Concepts, Single Event Effects
Characterization, FPGA Scrubbing, and
Other Use Cases Using Industry Product Examples

 

This tutorial will focus on fault-tolerance concepts to allow uninterrupted software execution in the presence of correctable errors and SEE characterization results with the GR740 SoC and GR716 Microcontroller as product examples. The tutorial will also cover the development of the GRSCRUB FPGA scrubber IP core and its planned inclusion in the GR716 flight models.

 


Lucas Tambara

Cobham Gaisler

Lucas Antunes Tambara is a Component Engineer at Cobham Gaisler, Gothenburg, Sweden. He received his Ph.D. in Microelectronics and M.Sc. in Electrical Engineering from Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. He received his B.Sc. in Computer Science from Universidade Federal de Santa Maria (UFSM), Santa Maria, Brazil. His interests include radiation effects on integrated circuits, fault tolerance, embedded systems, and hardware design. Lucas has authored several publications in IEEE transactions and conferences, and also serves in the reviewer board of several international journals and frequently in the technical program committee for the RADECS and NSREC conferences.
 

 

 

Better FPGA Verification with Open Source
VHDL Verification Methodology (OSVVM)

 

Verification consumes a considerable amount of the FPGA development cycle. Using an effective verification methodology is important as it can improve the overall productivity and contribute to the success of a project.

Open Source VHDL Verification Methodology (OSVVM) accelerates your FPGA and ASIC verification project by providing utility and model (Verification IP) libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. (see extended abstract for more details)

 


 

Jim Lewis

SynthWorks

Jim Lewis has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.
 

Paul Armijo
GSI Technology

 

George Williams
GSI Technology

 

 

 

AI Journeys to Space

 

 

AI is everywhere. In our phones, in our homes, where we work, where we play. The "new industry revolution" in AI and machine learning, fueled by the "new oil" - massive amounts of data - has spread globally with alarming speed. But, AI has rarely left earth’s orbit, and it’s non-existent in deep space craft. The most recent Mars Rover runs on 15 year old CPU technology. Recently launched spacecraft lack the ability to navigate themselves, requiring constant communication with ground control. Meanwhile, back on earth, humans are already riding in self-driving vehicles, and earthlings routinely run billion-parameter neural networks at real-time speeds.

Disruptive change is on its way, and it's happening at the intersection of space and artificial intelligence. Get ready. AI is soon going where no AI has gone before!

 


 

 

Paul Armijo is the Director of Aerospace & Defense Business Sector at GSI Technology, an embedded hardware and artificial intelligence company. Paul has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community, including roles as the Sr. Director of Systems Development Engineering and Government Programs at Cobham. Prior roles include Advanced Technology Development Manager at General Dynamics, Electrical Systems Lead Engineer on Kepler at Ball Aerospace, Technical Program Manager and Design Lead Engineer on numerous satellite programs at Northrop Grumman Innovation Systems as well as IC Design & Test Engineer at NXP. Paul received his B.S. in Electrical Engineering from Arizona State University.

 

George William is Director of Computing and Data Science at GSI Technology. He's held senior leadership roles in software, data science, and research, including tenures at Apple's New Product Architecture group and at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, software development, cybersecurity, and compute hardware. He is an author on several research papers in computer vision and deep learning, published and presented at NeurIPS, CVPR, ICASSP, SIGGRAPH, Space Computing, and RHET.

 

 

 

 

Welcome Our 2020 Virtual Exhibitors

2020 SEE/MAPLD Virtual Supporter/Exhibitor Registration is now closed.
Please contact Teresa Farris if you have any questions.


Teresa Farris
Archon, LLC
Teresa.Farris@archon-llc.com

Supporters / Exhibitors
Lattice Semiconductor Logo

Double Exhibit
Lattice Semiconductor

contact: Jim Tavacoli
phone: 415-717-3149
email: Jim.tavacoli@latticesemi.com
web: www.latticesemi.com
3D Plus Logo
3D Plus
contact: Timothee Dargnies
phone: 510-824-5591
email: dcollins@3d-plususa.com
web: www.3d-plus.com
Ultra Tec Logo
ASAP-1 - ULTRA TEC
contact: Tim Hazeldine
phone: 714-542-0608
email: tim@ultratecusa.com
web: www.ultratecusa.com
Cobham Gaisler AB Logo
Cobham Gaisler
contact: Sandi Habinc
email: Sandi@gaisler.com
phone: 011-46-70-795-0381
web: www.cobham.com/gaisler

EMPC Logo

EMPC
contact: Larisa Milic
email: lmilic@empc.com
phone: 301-869-2317
web: www.empc.com
GSI Technology Logo
GSI Technology
contact: Paul Armijo
phone: 408-331-9863
email: parmijo@gsitechnology.com
web: www.gsitechnology.com
Mentor Logo

Mentor, A Siemens Business
contact: Melissa Ferro
email: melissa_ferro@mentor.com
phone: 510-354-5878
web: www.mentor.com
NASA Electronic Parts and Packaging Program Logo

NASA Electronic Parts and Packaging (NEPP) Program
contact: Jonny Pellish
email: jonathan.pellish@nasa.gov
phone: 301-286-1852
web: nepp.nasa.gov
Northwestern Medicine Proton Center Logo

Northwestern Medicine Proton Center
contact: Steve Laub
email: steven.laub@nm.org
phone: 630-821-6376
web: www.protoncenter.nm.org
Radiation Test Solutions Logo

Radiation Test Solutions, Inc.
contact: Malcolm Thomson
email: mthompson@radiationtestsolutions.com
phone: 719-339-3146
web: www.radiationtestsolutions.com
Renesas Electronics America Logo
Renesas Electronics America
contact: Eric Thomson
phone: 321-724-7247
email: eric.thomson.eb@gr.renesas.com
web: www.renesas.com
STAR-Dundee Logo
STAR-Dundee
contact: Alberto Gonzalez Villafranca
email: alberto.gonzalez@star-dundee.com
phone: +44 1382 201755
web: www.star-dundee.com
Cobham Advanced Electronic Solutions Logo
Cobham Advanced Electronic Solutions
contact: Tony Jordan
phone: 719-594-8252
email: tony.jordan@cobham.com
web: www.cobham.com/CAES

Integra Logo
Integra Technologies
contact: Ted Barlett
email: ted.barlett@integra-tech.com
phone: 316-630-6801
web: www.integra-tech.com
EPC Space Logo
EPC Space
contact: Max Zafrani
phone: 978-620-8271
email: sales@epc.space
web: epc.space
Traditional Exhibitors
 
Tortuga Logic Logo


Tortuga Logic
contact: Jennifer Spangle
phone: 888-488-7706
email: jennifer@tortugalogic.com
web: http://www.tortugalogic.com
Blue Pearl Software Logo
Blue Pearl Software
contact: Jennifer Treiber
email: jenn.treiber@bluepearlsoftware.com
phone: 408-961-0121
web: www.bluepearlsoftware.com

Topline Logo
TopLine
contact: Martin Hart
email: info@topline.tv
phone: 800-776-9888
web: www.topline.tv
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Crocker Nuclear Laboratory, UC Davis
contact: Eric Prebys
email: eprebys@ucdavis.edu
phone: 530-771-7024
web: crocker.ucdavis.edu
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Robust Chip, Inc.
contact: Klas Lilja
phone: 925-425-0820
email: klas.lilja@robustchip.com
web: www.robustchip.com
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Oak Ridge National Laboratory Spallation Neutron Source
contact: Bernie Riemer
phone: 865-574-6502
email: riemerbw@ornl.gov
web: neutrons.ornl.gov/sns
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SynthWorks
contact: Jim Lewis
phone: 503-590-4787
email: jim@synthworks.com
web: synthworks.com
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Scientic
contact: Bryan Hughes
phone: 256-319-0800
email: Bryan.Hughes@scientic.com
web: www.scientic.com
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Silicon Technologies, Inc.
contact: Ken Potts
phone: 385-695-5904
email: sales@silicontechnologiesinc.com
web: silicontechnologiesinc.com

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TRAD Tests & Radiation
contact: Christian Chatry
phone: +33 5 61 00 95 60
email: christian.chatry@trad.fr
web: www.trad.fr
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Flex Logix
contact: Andy Jaros
phone: 925-785-3016
email: andy@flex-logix.com
web: www.flex-logix.com
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Allied Scientific Pro
contact: Steeve Lavoie
phone: 800-253-4107
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web: www.alliedscientificpro.com

2020 Virtual SEE/MAPLD Workshop Registration Procedures

Ground Rules For All Attendees
Attendee registration is open from August 27 to December 15, 2020.

Attendees will receive an instructional email from "SEE/MAPLD 2020 <2020NoReplyengagez.com>"

Please watch for this prior to the event!

Registrations cannot be shared
Registration for Attendees and Exhibitors

Registration Option Fee
Technical $225.00
Full-Time Retiree $100.00
Full-Time Student $50.00
Note: There is no Guest Registration for 2020

Attendees - CLICK HERE - to Register

Registration for Supporter/Exhibitors and Exhibitors

SEE/MAPLD is adding a special Supporter/Exhibitor category for the Virtual Event!
SEE/MAPLD Virtual Supporter/Exhibitor is $2000 with 8 Virtual Technical Registration Comps

SEE/MAPLD Virtual Exhibitor-Only is $1000 with 4 Virtual Technical Registration Comps
No staff only badges for the Virtual Event

Virtual Supporter/Exhibitor Registration ended on Sept 14, 2020

Official SEE/MAPLD Registration Cancellation Policy (Technical and Exhibits)

There are no refunds for the 2020 SEE/MAPLD Virtual Event

Hotel Reservation Cancellation


Please refer to our Hotel Information page regarding cancellation of hotel reservations

If you have made a reservation for the 2020 SEE/MAPLD at the La Jolla Marriott, you MUST cancel. The Hotel will not automatically cancel outstanding reservations.

Visit the Marriott Website

Previous SEE Symposium and SEE/MAPLD Home Pages: 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019

SEE Symposium and SEE/MAPLD Presentation Materials 2006-2019

Contact Us

General Chair(s): SEE: David Hansen, Data Device Corporation / MAPLD: Gregory Allen, NASA/JPL-Caltech
Technical Program Chair(s): SEE: Megan Casey, NASA Goddard Space Flight Center / MAPLD Co-Chairs: Nadia Rezzak, Microchip Technology, Inc. and Pierre Maillard, Xilinx
Poster Session Chair: Martha O'Bryan, SSAI / NASA Goddard Space Flight Center
Industrial Exhibit Chairwoman: Teresa Farris, Archon, LLC
Local Arrangements & Registration Services: Teresa Farris, Archon, LLC
Website Curator: Carl Szabo, SSAI / NASA Goddard Space Flight Center

SEE/MAPLD Code of Conduct

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