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Welcome to the homepage of the 30th Annual Single Event Effects (SEE) Symposium
coupled with the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop

The 2021 SEE/MAPLD Workshop will be held as a virtual meeting
during the week of August 30, 2021

Registration details to follow

The call for papers is open at the menu link above
Abstract submission deadline is April 16, 2021

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Featuring over 700 talks spanning years 2006-2019
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Please join us during the week of August 30th, 2021 for the virtually held

2021 Single Event Effects (SEE) Symposium and Military and Aerospace
Programmable Logic Devices (MAPLD)

We are seeking contributions in the following areas, but all submissions will be reviewed. Four sessions are available: SEE, MAPLD, Combined, and Poster. The Combined Session includes submissions that cross SEE and MAPLD themes. The Poster Session can include SEE, MAPLD, or Combined content. Please refrain from technical content reasonably classified as product marketing.

Acknowledging the events of the past year, our technical chairs especially encourage the submission of content focusing on:
1) Standards & Methods 4) Modeling and Simulation
2) Alternatives to Heavy Ion and Proton Testing 5) Relevant Test Facility Updates
3) Space Environments

Submit Your Abstract Here

Deadline is April 16, 2021
SEE Symposium MAPLD
New! Artificial Intelligence (AI) / Machine Learning (ML) in FPGAs/SoCs: AI / ML design considerations for reliable terrestrial, avionic, and aerospace applications; using AI for SEE mitigation; SEE evaluation of designs leveraging AI / ML
Phenomena: Upsets, Functional Interrupts, Transients, Latchup, Gate Rupture, Burnout, etc. FPGAs/SoCs, PLDs, and New Devices: New and/or novel FPGA and PLDs; Benchmarking of FPGAs and PLDs; Applications of space-borne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Charge Transport and Collection, Impact of Circuit and Environmental Parameters, etc. Mitigation of Single event effects in FPGAs/SoCs, PLDs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), upset mitigation techniques and automated tools, etc.
SEE Mitigation Methods Including Radiation Hardened by Design (RHBD) and by Process (RHBP): Approaches for gaining SEE hardness in commercial devices, etc. Designing with FPGAs/SoCs, and PLDs: agile methods, ESL/HLS and model-based engineering techniques, embedded processing, and synthesis efficiency improvements.
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Pulsed Laser Test Facilities. Validation and Verification of FPGAs/SoCs, and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices from LEO to Interplanetary, High Altitude Aircraft, and Terrestrial. Availability/Reliability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data and Measurement Techniques: Memories, Analog/Digital Circuits, systems-on-chip (SoCs), Field Programmable Gate Arrays (FPGAs), Optocouplers, Photonic Integrated Circuits, Power Converters, Sensors, etc. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, etc.
Systems and Error Rate Computation: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems; Analytic, Monte Carlo, Mixed-Level, methods, etc. Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Education: Education Practices, Market Demands for Military and Aerospace Component Engineers, and Engineer Retention.
*All options subject to change any time, per the discretion of the conference committee

The 2021 Preliminary Program will become available after abstract submission and review has completed

Details about our tutorial sessions coming soon.

2021 Exhibitors Coming Soon. For further details, please contact:
Teresa Farris
Archon, LLC

Registration Details for 2021 TBD

Hotel Details for 2021 TBD

Previous SEE Symposium and SEE/MAPLD Home Pages: 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019

SEE Symposium and SEE/MAPLD Presentation Materials 2006-2019

Contact Us

General Chair(s): SEE: Megan Casey, NASA Goddard Space Flight Center / MAPLD: Nadia Rezzak, Microchip Technology and Pierre Maillard, Xilinx, Inc.
Technical Program Chair(s): SEE: Rebekan Austin, NASA Goddard Space Flight Center and Steven LaLumondiere, The Aerospace Corporation / MAPLD: Tyler Lovelly, Air Force Research Laboratory
Poster Session Chairwoman: Martha O'Bryan, SSAI / NASA Goddard Space Flight Center
Industrial Exhibit Chairwoman: Teresa Farris, Archon, LLC
Local Arrangements & Registration Services: TBD
Website Curator: Carl Szabo, SSAI / NASA Goddard Space Flight Center

SEE/MAPLD Code of Conduct

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