2023 SEE/MAPLD Workshop Call for Papers
We are seeking contributions in the following areas, but all submissions will be reviewed. Four sessions are available: SEE, MAPLD, Combined, and Poster. The Combined Session includes submissions that cross SEE and MAPLD themes. The Poster Session can include SEE, MAPLD, or Combined content. Please refrain from technical content reasonably classified as product marketing.
We especially encourage the submission of content focusing on:
1) Standards & Methods 4) Modeling and Simulation
2) Alternatives to Heavy Ion and Proton Testing 5) Relevant Test Facility Updates
3) Space Environments  
Abstract Submission Guidelines:

We accept Microsoft Word .docx, Microsoft Powerpoint .pptx, or Adobe .pdf only.

If you choose to submit a Word or PDF abstract: Please keep submission to a minimum of 1 and a maximum of 4 pages.

If using PowerPoint, your charts should provide a title page with authors and affiliations,
motivation / context / overview, available relevant results, and anticipated conclusions.

To get started, please make use of our supplied templates:


Submission Deadline Has Passed
The conference committee will attempt to notify all prospective speakers of acceptance status by March 31st.
 
SEE Symposium / Combined* / MAPLD Session Options
New! Artificial Intelligence (AI) / Machine Learning (ML) in FPGAs/SoCs: AI / ML design considerations for reliable terrestrial, avionic, and aerospace applications; using AI for SEE mitigation; SEE evaluation of designs leveraging AI / ML
Phenomena: Upsets, Functional Interrupts, Transients, Latchup, Gate Rupture, Burnout, etc. FPGAs/SoCs, PLDs, and New Devices: New and/or novel FPGA and PLDs; Benchmarking of FPGAs and PLDs; Applications of space-borne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Charge Transport and Collection, Impact of Circuit and Environmental Parameters, etc. Mitigation of Single event effects in FPGAs/SoCs, PLDs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), upset mitigation techniques and automated tools, etc.
SEE Mitigation Methods Including Radiation Hardened by Design (RHBD) and by Process (RHBP): Approaches for gaining SEE hardness in commercial devices, etc. Designing with FPGAs/SoCs, and PLDs: agile methods, ESL/HLS and model-based engineering techniques, embedded processing, and synthesis efficiency improvements.
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Pulsed Laser Test Facilities. Validation and Verification of FPGAs/SoCs, and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices from LEO to Interplanetary, High Altitude Aircraft, and Terrestrial. Availability/Reliability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data and Measurement Techniques: Memories, Analog/Digital Circuits, systems-on-chip (SoCs), Field Programmable Gate Arrays (FPGAs), Optocouplers, Photonic Integrated Circuits, Power Converters, Sensors, etc. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, etc.
Systems and Error Rate Computation: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems; Analytic, Monte Carlo, Mixed-Level, methods, etc. Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Education: Education Practices, Market Demands for Military and Aerospace Component Engineers, and Engineer Retention.
*All options subject to change any time, per the discretion of the conference committee